A Programmable System with Quick Reconfiguration

This paper presents a Micro-Sequencer based reconfigurable system. We introduce the concept of Quick Reconfiguration and compare it with existing “full reconfiguration” schemes. In a typical scenario, reconfiguring a system from one application to another does not require a “full” reconfiguration. Instead we can exploit similarities among various applications to save on reconfiguration time. This task can be accomplished via micro-programming of a micro-sequencer architecture. We show that a significant speed up is gained by reconfiguring a system on a set of image processing benchmarks, which takes hundreds of μseconds versus hours in traditional FPGA reconfigurations. Furthermore, by using this architecture, it has been shown that other parameters of system, for instance the size of data bus, can be easily modified to customize the system for a specific application. This results in significant improvements in power consumption, speed and silicon area. Experimental results show that power consumption and silicon area are reduced by 72% and 77% respectively by using a customized 8-bit data bus versus 64-bit data bus while the speed is improved by 157%. Roozbeh Jafari Roozbeh Jafari received his B.S. in Electrical Engineering in 2000 from the Sharif University of Technology, Tehran, Iran. He joined the State University of New York at Buffalo,NY in 2000 and received his M.S. in Electrical Engineering in 2001. His main research focus was VLSI Testing and Verification. He also worked at IBM, Endicott, NY on development of the IBM TestBench tool designed for VLSI Testing. He is currently pursuing his Ph.D. degree in Computer Science at the University of California, Los Angeles, CA. He is a member of the ER group working under the supervision of Professor M. Sarrafzadeh. Henry Fan Henry Fan received his B.S. in 1998 from University of California at Berkeley. In 2001, he joined the ER group in UCLA. He worked under the supervision of Professor Majid Sarrafzadeh and received his M.S. in 2002. He research topics were mainly focused on reconfigurable devices and high-level synthesis. Majid Sarrafzadeh Majid Sarrafzadeh (http://www.cs.ucla.edu/~majid) received his B.S., M.S. and Ph.D. in 1982, 1984, and 1987 respectively from the University of Illinois at Urbana-Champaign in Electrical and Computer Engineering. He joined Northwestern University as an Assistant Professor in 1987. In 2000, he joined the Computer Science Department at University of California at Los Angeles (UCLA). His recent research interests lie in the area of Embedded and Reconfigurable Computing, VLSI CAD, and design and analysis of algorithms. Dr. Sarrafzadeh is a Fellow of IEEE for his contribution to "Theory and Practice of VLSI Design". He received an NSF Engineering Initiation award, two distinguished paper awards in ICCAD, and the best paper award in DAC. He has served on the technical program committee of numerous conferences in the field. Professor Sarrafzadeh has published approximately 250 papers, is a co-editor of the book "Algorithmic Aspects of VLSI Layout" (1994 by World Scientific), and co-author of the book "An Introduction to VLSI Physical Design" (1996 by McGraw Hill). Dr. Sarrafzadeh is on the editorial board of the VLSI Design Journal, an Associate Editor of ACM Transaction on Design Automation (TODAES) and an Associate Editor of IEEE Transactions on Computer-Aided Design (TCAD).